The miniaturization of CMOS devices has hitherto been governed by a trend—often called Moore's law—in which electronic components shrink in size by half every 2 years. The International Technology Roadmap for Semiconductors (ITRS) has established a projected growth curve according to this model. The demands for speed, high integration level, high performance and low production costs attendant on such a rate of progress are very stringent. Consequently, the problems associated with the demand in decreasing feature size have escalated and among many problems, lithographically transferring pattern at the nanoscale is eminent. Hence there is a need to search for alternative solutions to the problems that will ultimately impede the progress of silicon technology in the immediate future. This means that devising new method of low cost, mass production compatible pattern transfer solution is critical to sustaining the projected rate of growth. Lithography is an important process when manufacturing integrated circuits, and is used to transfer patterns from layer to layer. Today's widespread used optical lithography technology is approaching its fundamental limits governed by the optics, wave length, lens etc. and has to rely on expensive equipment to coup up with present demands. One alternative to such traditional lithography method is nanoimprint lithography described in patent U.S. Pat. No. 5,772,905, where a stamp with nanoscale features is pressed into a thermoplastic polymer. In this particular patent, the stamp was made by etching the substrate to create the patterns to be transferred and typical metal, dielectric or semiconductor bulk material are used for creating the mold. The stamp is sometimes labeled mould, mould, die or template, and nanoimprint lithography is sometimes referred to as “imprint lithography”. The polymer is heated while imprinted with the stamp. After cooling the stamp is removed from the polymer, which now has imprinted nanoscale features. This process is described in FIG. 1, where the stamp 100 has protrusions 102. These protrusions are typically manufactured from silicon based material.
A wafer 105 with a layer 104 to be patterned and a deposited resist layer 103 is also seen in the FIG. 1A. FIG. 1B shows the stamp pressed toward the polymer coated wafer, which has been heated to a temperature above the glass transition temperature of the polymer. After cooling, the stamp is lifted and depressions 107 are present in the now patterned resist layer 103, as seen in FIG. 1C. Plasma etching is utilized to remove the unwanted residuals to achieve 108 of the polymer layer, see FIG. 1D. Using the polymer as a mask, the layer 104 (into 109) is patterned by etching and the result is seen in FIG. 1E. The remaining polymer is removed, as seen in FIG. 1F. Instead of etch back processing, a lift-off processing can be used. Then the metal layer is deposited on top of the patterned resist layer, and the unwanted parts of the metal layer (which is on top of the resist) are removed by lifting off the resist.
Today's nanoimprinting stamps suffer from poor releasing mechanism from the resist layer. However, several improvements of the technique have been presented in patent U.S. Pat. No. 6,309,580 where they have described the use of an anti-sticking material applied to the stamp, to improve the release properties. To increase the releasing properties even further, in WO2006/028282 carbon nanowalls are used on the mold. Another improvement of stamps life time was described in the patent U.S. Pat. No. 7,080,596 by using SiC substrate as stamp material. A third improvement of the stamp is described in paten U.S. Pat. No. 6,943,117 where Ultra violet radiation (UV) imprint lithography is introduced in order to avoid pressure and issues due to contacting during standard nanoimprint. In this method a transparent substrate is used and implementing high pressure is avoided. However, the method is limited to working only for UV transparent substrates.
A grown nanostructure is an object of intermediate size between molecular and microscopic (micrometer-sized) structures. The last decade a number of different types of nanostructures have been investigated. One important aspect of the nanostructures is its anisotropic properties, meaning the properties vary substantially in different direction of the structures. For example, carbon nanostructures are considered to be one of the most promising candidates for future developments in nano-electronics, nano-electromechanical systems (NEMS), sensors, contact electrodes, nanophotonics, and nano-biotechnology. This is due principally to their one dimensional nature, and their unique electrical, optical and mechanical properties. Carbon nanotubes and carbon nanofibers have been considered for both active devices and as interconnect technology at least because their electrical and thermal properties and their strength. For example, the high electron mobility of carbon nanotubes (79,000 cm2/Vs) surpasses that of state-of-the-art MOSFET devices. Finally, high E-modulus (representing the strength of a material) of individual nanostructures as high as 1 TPa have been reported along its axis. However, the E-modulus in transverse axis is orders of magnitude smaller. Therefore, carbon nanotubes and carbon nanofibers are a good choice for applications where high strength is required.
However, to our knowledge, no one has recognized the use of grown nanostructures as apparatus for manufacturing template/mold/apparatus for imprint technology to provide high aspect ratio, recyclable, reworkable templates/mold/apparatus with a resolution covering from macro scale down to a nanometer scale. Furthermore, the possibility of developing a lithographic method that combines imprint technology and nanostructure growth technologies to replace the conventional lithography technologies used in industries has never been recognized.
Moreover, a template with nanostructures has never been used for perforating a substrate.